The development of information-oriented society in recent years has been dramatic, and in the field of information processing instruments, an improvement in functions of the instruments has been desired whether the instruments are large or small in size. In the field of, for example, household instruments, with regard to personal computers, portable telephones and other instruments, the size and the weight thereof are being made smaller and the performance and the function thereof are being made higher. In the field of industrial equipment, with regard to wireless base stations, optical communication devices, network-related instruments such as servers and routers, and others, the same as described above are being investigated. Moreover, with an increase in the quantity of transmitting-information, there manifests a tendency that the frequency of signals handled in information processing instruments is being made higher year by year; thus, high-speed processing and high-speed transmitting techniques are also being developed. For example, with regard to packaging- or mounting-related technique, LSIs such as CPUs, DSPs and various memories have been made higher in processing-speed and function, and further as new high-density mounting techniques, system-on-chips (SoC), system-in-packages (SiP), and others have been actively developed. In such a situation, semiconductor chip mounting boards or mother boards also need to correspond to the rise or improvement in the frequency, the wiring density and the function. In recent years, as a typical matter which constitutes each of these boards, use has been made of multi-level (or multilayered) wiring boards of a build-up type which are formed to have fine wiring (i.e., fine interconnections) wherein the line/space width (L/S) is “15 μm/15 μm”, or less.
The formation of fine wiring on a substrate is usually attained with the subtractive process or the semi-additive process. In an ordinary wiring-forming step based on the subtractive process, an etching resist is first formed on a copper surface, and then the workpiece is exposed to light and developed to form a resist pattern. Next, unnecessary portions of copper are etched, and the resist is peeled to form a wiring. Meantime, in an ordinary wiring-forming step based on the semi-additive process, a plating resist is first formed on a copper (seed layer) surface, and then the workpiece is exposed to light and developed to form a resist pattern. Next, the workpiece is subjected to electroplating, resist-peeling and etching treatments to form a wiring. Whether any one of the processes is used, a solder resist or coverlay can be optionally formed on the wiring after the formation of the wiring in order to protect the wiring on regions other than regions of terminals such as external connection terminals and semiconductor chip connection terminals.
In order to use any one of the processes to make a fine wiring formation ratio corresponding to a design value of the L/S width, it is necessary to form a resist pattern as designed. However, in the formation of fine wiring wherein the L/S=“15 μm/15 μm”, or less, it is difficult that the precision of the resist pattern is made high since the precision is affected by the following matter: when the workpiece is exposed to light, halation is caused on its glossy copper surface by light reflection. Moreover, the adhesive force between the copper surface and the resist pattern is low so that the resist pattern is easily peeled when a wiring is formed. Furthermore, a sufficient bonding property (adhesiveness) tends not to be gained between the wiring (copper) and the solder resist or between the wiring and the coverlay. In order to solve these problems, it is important to remove the glossiness of the copper surface and heighten the adhesive force between the copper surface and the resist.
Apart from the above, a multi-level wiring board of a build-up type is produced by repeating an interlayer-dielectric-forming step and a wiring-forming step mutually. When this producing method is used, it is important to certainly keep the bonding strength between the wiring and the insulating resin, the insulation reliability between the wiring pieces, and the wiring precision. In order to improve such various properties, investigations have been hitherto made about several methods related to copper surface treatment.
A first thereof is related to a method of giving a form of roughening-irregularities in the order of micrometers to copper surface to remove the glossiness of copper surface, and further yielding a bonding force between the copper surface and a resist or between the copper surface and an insulating resin besides the resist by anchor effect. As an example thereof, Patent document 1 discloses a method of giving a form of roughening-irregularities in the order of micrometers to a copper surface by use of an aqueous solution containing a main agent composed of an inorganic acid and a copper oxidizing agent, and an auxiliary composed of at least one azole and at least one etching restrainer. As another example thereof, Patent document 2 discloses a method of forming continuous irregularities having heights of 1.5 to 5.0 μm by micro etching, and then subjecting the workpiece to chromate treatment and coupling agent treatment.
A second of the methods is related to a method of forming fine irregularities made of needle crystals of copper oxide onto the copper surface, subjecting the workpiece to reducing treatment to yield fine metallic copper needle crystals, next removing the glossiness of the copper surface, and further yielding bonding force between the copper surface and a resist or between the copper surface and an insulating resin by anchor effect. As an example thereof, Patent document 3 discloses a method of using an aqueous alkaline solution containing an oxidizing agent such as sodium chlorite, immersing metallic copper into the aqueous solution at about 80° C. to give fine needle crystals of copper oxide onto the surface, and subsequently using an acidic solution wherein at least one amine borane is mixed with a boron-based agent to subject the workpiece to reducing treatment, thereby yielding fine needle crystals of metallic copper.
A third thereof is related to a method of forming a nobler metal than copper discretely onto the copper surface, oxidizing the copper to form irregularities made of needle crystals of copper oxide, and then subjecting the workpiece to reducing treatment to give, thereto, nano-level irregularities made of metallic copper needle crystals, and further yielding bonding force between the copper surface and an insulating resin by anchor effect. Such a method is disclosed in Patent document 4.